This application claims priority of European Patent Application No. 98306189.6, which was filed on Aug. 04, 1998.
The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop.
Phase detectors realized with a flip-flop are known in the art. German Patent DE 40 16 429 C2, which is incorporated by reference herein, shows a phase detector being realized with a D-type flip-flop. A feedback clock is coupled to a clock input of the flip-flop. A reference clock is coupled via a mono-flop, which generates a pulse, to asynchronously reset the input of the flip-flop. The output of the flip-flop is a control signal for controlling, such as, for example, a voltage controlled oscillator. The data input of the flip-flop is coupled to the inverted output of the flip-flop.
Referring to FIG. 1, a phase locked loop (PLL) having the known phase detector is illustrated. The PLL consists of a voltage controlled oscillator 1, a PLL filter, a D-type flip-flop 2 forming the known phase detector, a low pass filter 3 and a mono-flop 4. A clock signal FB produced by the voltage controlled oscillator 1, being the feedback dock, is coupled to a clockk input C of flip-flop 2 and a pulse RES. derived, for example from the rising edge of a reference clock REF by mono-flop 4, is coupled to an asynchronous reset input R of flip-flop 2. A data input D of flip-flop 2 is coupled to an inverse output Q"" of the flip-flop 2. Therefore, an output signal OUT at output Q of the flip-flop 2, forms a control signal which goes to a high level, such as a system voltage, with the rising edge of the feedback clock FB, and goes to a low level with the rising edge of the reference clock REF.
The output signal OUT is filtered by the low pass filter 3 consisting of a resistor R1 and a capacitor C1, and forms a control signal OUT3 for the voltage controlled oscillator 1, which corresponds to the mean value of the output signal OUT, formed by the low pass filter 3. A useful nominal operating point is given by a duty cycle of 1:1. Other operating points are also possible. Phase delay between the reference clock REF and the feedback clock FB is then given with a phase of xcfx80 in a locked high gain PLL circuit.
In case of a reference clock REF failure the signal RES goes inactive, the flip-flop 2 works as a divider by two. Therefore the output signal OUT has a duty cycle of exactly 1:1, i.e. the phase detector 2 works at the nominal operating point. For that reason the phase detector formed by flip-flop 2 is self biasing in case of loss of the reference clock REF.
FIG. 2 shows the transfer function of the phase detector, i.e. the phase deviation xcfx86 of reference clock REF to feedback clock FB versus the filtered phase detector output signal OUT3. The phase detector uses almost the whole phase deviation from O to 2xcfx80 for detection. There is only a small and well defined dead-zone Z caused by the pulse width of the reset pulse RES derived from the reference clock REF by mono-flop 4. As long as the reset pulse RES is active, the feedback clock FB on the clock input C of the flip-flop 2 cannot set the output Q of the flip-flop 2. Therefore, the state of output Q is well defined under all conditions, including a phase difference 0 of reference and feedback clock.
However, the proposed generation of the reset pulse RES for the phase detector flip-flop 2 has the disadvantage, that the mono-flop 4 has to be dimensioned in a way that the reset pulse RES generated is neither to short nor to long. If it is to short the phase detector flip-flop 2 will not be reset. If it is too long the dead-zone Z will be unnecessarily long. In addition it has to be secured, so that no matter how the reference clock signal REF failsxe2x80x94static high or static low, the signal at the reset input R of the phase detector flip-flop 2 goes inactive (low).
Another drawback of the known phase detector flip-flop 2 is that a skew (phase error) is present. The skew depends on the different delay times of the clock to data valid transition, i. e. the delay caused by the phase detector flip-flop 2 after a rising edge of the feedback clock FB, and of the reset to data valid transition, i. e. the delay caused by the mono-flop 4 and the phase detector flip-flop 2 after a rising edge of the reference clock REF.
Accordingly, it is an object of the present invention to provide a phase detector being formed by a flip-flop. It is the aim of the inventive phase detector under consideration to avoid the drawbacks known from the state of the art.
The object is achieved by providing a phase detector having a D-flip-flop with a first output for a control signal, a first input for a feedback clock, a second input for a pulse, generated from a reference clock and a third input to which a second output is coupled, by a gate for generating the pulse from the reference clock and that an output of said gate is coupled back to an input of said gate.
An advantage of the present invention is that it provides a reset pulse for a phase detector being formed by a D-flip-flop that has an optimum width, without the necessity of explicitly dimensioning it. Another advantage of the present invention is that it allows the design of a skewless phase detector.
The present invention will become more fully understood from the detailed description given hereinafter and further scope of applicability of the present invention will become apparent. However, it should be understood that the detailed description is given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art.